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1 ? fn6357.1 isl54056 ultra low on-resistance, +1.65v to +4.5v, single supply, quad spdt (dual dpdt) analog switch the intersil isl54056 device is a low on-resistance, low voltage, bidirectional, quad spdt (dual dpdt) analog switch designed to operate from a single +1.65v to +4.5v supply. targeted applications include battery powered equipment that benefit from low r on (0.39 ) and fast switching speeds (t on = 30ns, t off = 16ns). the digital logic input is 1.8v logic-compatible when using a single +3v supply. with a supply voltage of 4.2v and logic high voltage of 2.85v at both logic inputs, the part draws only 12a max of icc current. cell phones, for example, often face asic functionality limitations. the number of analog input or gpio pins may be limited and digital geometries are not well suited to analog switch performance. this part may be used to ?mux-in? additional functionality while reducing asic design risk. the isl54056 is offered in small form factor package, alleviating board space limitations. the isl54056 consists of four sp dt switches. it is configured as a dual double-pole/double-throw (dpdt) device with two logic control inputs that control two spdt switches each. the configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer. the isl54056 is pin compatible with the nlas3799 and nlas3799l. features ? pb-free plus anneal available (rohs compliant) ? pin compatible replacement for the nlas3799 and nlas3799l ? on resistance (r on ) - v+ = +4.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39 - v+ = +3.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45 - v+ = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 ?r on matching between channels . . . . . . . . . . . . . . . . 0.05 ?r on flatness across signal range . . . . . . . . . . . . . . . 0.05 ? single supply operation . . . . . . . . . . . . . . . +1.65v to +4.5v ? low power consumption (pd) . . . . . . . . . . . . . . . . <0.68 w ? fast switching action (v+ = +4.3v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns ? break-before-make ? 1.8v logic compatible (+3v supply) ? low icc current when vinh is not at the v+ rail ? available in 16 ld 2.6x1.8x0.5mm tqfn ? esd hbm rating - com pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kv - all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kv applications ? battery powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? table 1. features at a glance isl54056 number of switches 4 sw quad spdt (dual dpdt) 4.3v r on 0.39 4.3v t on /t off 30ns/16ns 3.0v r on 0.45 3.0v t on /t off 34ns/18ns 1.8v r on 0.65 1.8v t on /t off 48ns/23ns package 16 ld 2.6x1.8x0.5mm tqfn data sheet october 30, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6357.1 october 30, 2006 pinouts (note 1) isl54056 (tqfn) top view note: 1. switches shown for logic ?0? input. 1 3 4 15 nc1 in1-2 no2 com2 com1 no1 v+ nc4 16 14 13 2 12 10 9 11 6 578 com4 no4 in3-4 nc3 nc2 gnd no3 com3 truth table logic nc sw no sw 0onoff 1offon note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions pin function v+ system power supply input (+1.65v to +4.5v) gnd ground connection in digital control input com analog switch common pin no analog switch normally open pin nc analog switch normally closed pin ordering information part number part marking temp. range (c) package pkg. dwg. # ISL54056IRUZ-T (note) gaa -40 to 85 16 ld thin qfn tape and reel (pb-free) l16.2.6x1.8a note: intersil pb-free plus anneal products em ploy special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl54056
3 fn6357.1 october 30, 2006 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7v input voltages no, nc, in (note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) output voltages com (note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) continuous current no, nc, or com . . . . . . . . . . . . . . . . . 300ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . 500ma esd rating: hbm com x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kv hbm no x , nc x , in x , v+, gnd . . . . . . . . . . . . . . . . . . . . . . .>6kv mm com x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700v mm no x , nc x , in x , v+, gnd . . . . . . . . . . . . . . . . . . . . . . .>300v cdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kv thermal resistance (typical, note 3) ja (c/w) tqfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . +300c (lead tips only) operating conditions temperature range isl54056iruz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 2. signals on nc, no, in, or com exceeding v+ or gnd are clamped by internal diodes. limi t forward diode current to maximum curr ent ratings. 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v inh = 1.6v, v inl = 0.5v (note 4), unless otherwise specified parameter test conditions temp (c) (note 5) min typ (note 5) max units analog switch characteristics analog signal range, v analog full 0 v+ v on resistance, r on v+ = 3.9v, i com = 100ma, v no or v nc = 0v to v+ (see figure 5) 25 0.4 full 0.45 r on matching between channels, r on v+ = 3.9v, i com = 100ma, v no or v nc = voltage at max r on (note 7) 25 0.05 full 0.06 r on flatness, r flat(on) v+ = 3.9v, i com = 100ma, v no or v nc = 0v to v+ (note 6) 25 0.05 full 0.05 no or nc off leakage current, i no(off) or i nc(off) v+ = 4.5v, v com = 0.3v, 3v, v no or v nc = 3v, 0.3v 25 -70 70 na full -165 165 na com on leakage current, i com(on) v + = 4.5v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v 25 -70 70 na full -165 165 na dynamic characteristics turn-on time, t on v+ = 3.9v, v no or v nc = 3.0v, r l =50 , c l = 35pf (see figure 1) 25 33 ns full 38 ns turn-off time, t off v+ = 3.9v, v no or v nc = 3.0v, r l =50 , c l = 35pf (see figure 1) 25 16 ns full 21 ns break-before-make time delay, t d v+ = 4.5v, v no or v nc = 3.0v, r l =50 , c l = 35pf (see figure 3) full 3 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 248 pc off isolation r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 4) 25 65 db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 6) 25 -85 db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 0.008 % isl54056
4 fn6357.1 october 30, 2006 no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 38 pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 102 pf power supply characteristics power supply range full 1.65 4.5 v positive supply current, i+ v+ = +4.5v, v in = 0v or v+ 25 0.15 a full 1.4 a positive supply current, i+ v+ = +4.2v, v in = 2.85v 25 12 a digital input characteristics input voltage low, v inl full 0.5 v input voltage high, v inh full 1.6 v input current, i inh , i inl v+ = 4.5v, v in = 0v or v+ full -0.5 0.5 a notes: 4. v in = input voltage to perform proper function. 5. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 6. flatness is defined as the difference between maximum and minimum value of on-resi stance over the specified analog signal ran ge. 7. r on matching between channels is calculated by subtracting the channel with the highest ma x ron value from the channel with lowest max ron value, between nc1 and nc2, nc3 and nc4 or between no1 and no2, no3 and no4. electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 4), unless otherwise specified parameter test conditions temp (c) (note 5) min typ (note 5) max units analog switch characteristics analog signal range, v analog full 0 v+ v on resistance, r on v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+ (see figure 5) 25 0.45 0.55 full 0.65 r on matching between channels, r on v+ = 2.7v, i com = 100ma, v no or v nc = voltage at max r on (note 7) 25 0.05 0.12 full 0.15 r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+ (note 6) 25 0.07 0.15 full 0.15 no or nc off leakage current, i no(off) or i nc(off) v+ = 3.3v, v com = 0.3v, 3v, v no or v nc = 3v, 0.3v 25 1.1 na full 30 na com on leakage current, i com(on) v + = 3.3v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v, or floating 25 1.5 na full 45 na dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l =50 , c l = 35pf (see figure 1) 25 34 ns full 39 ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l =50 , c l = 35pf (see figure 1) 25 18 ns full 23 ns break-before-make time delay, t d v+ = 3.3v, v no or v nc = 1.5v, r l =50 , c l = 35pf (see figure 3) full 3 ns electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v inh = 1.6v, v inl = 0.5v (note 4), unless otherwise specified (continued) parameter test conditions temp (c) (note 5) min typ (note 5) max units isl54056
5 fn6357.1 october 30, 2006 charge injection, q c l = 1.0nf, v g = 0v, r g = 0 (see figure 2) 25 126 pc off isolation r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 4) 25 65 db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 6) 25 -85 db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 0.012 % no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 38 pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (see figure 7) 25 102 pf power supply characteristics positive supply current, i+ v+ = 3.6v, v in = 0v or v+ 25 0.021 a full 0.72 a digital input characteristics input voltage low, v inl full 0.5 v input voltage high, v inh full 1.4 v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -0.5 0.5 a electrical specifications - 1.8v supply test conditions: v+ = +1.65v to +2v, gnd = 0v, v inh = 1.0v, v inl = 0.4v (note 4), unless otherwise specified parameter test conditions temp (c) (note 5) min typ (note 5) max units analog switch characteristics analog signal range, v analog full 0 v+ v on resistance, r on v+ = 1.8v, i com = 100ma, v no or v nc = 0v to v+ (see figure 5) 25 0.65 0.8 full 0.85 dynamic characteristics turn-on time, t on v+ = 1.65v, v no or v nc = 1.0v, r l =50 , c l = 35pf (see figure 1) 25 50 ns full 55 ns turn-off time, t off v+ = 1.65v, v no or v nc = 1.0v, r l =50 , c l = 35pf (see figure 1) 25 25 ns full 30 ns break-before-make time delay, t d v+ = 2.0v, v no or v nc = 1.0v, r l =50 , c l = 35pf (see figure 3) full 8 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ( see figure 2) 25 48 pc digital input characteristics input voltage low, v inl full 0.4 v input voltage high, v inh full 1.0 v input current, i inh , i inl v+ = 2.0v, v in = 0v or v+ full -0.5 0.5 a electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 4), unless otherwise specified (continued) parameter test conditions temp (c) (note 5) min typ (note 5) max units isl54056
6 fn6357.1 october 30, 2006 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection figure 3a. measurement points c l includes fixture and stray capacitance. figure 3b. test circuit figure 3. break-before-make time 50% t off 90% v+ 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on () + ------------------------------ = switch input logic input v out r l c l com no or nc in 50 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v+ 0v c l v out r g v g gnd com no or nc v+ c logic input in 90% v+ 0v t d logic input switch output 0v v out logic input in com r l c l v out 35pf 50 no nc v+ gnd v nx c isl54056
7 fn6357.1 october 30, 2006 detailed description the isl54056 is a bidirectional, quad single pole/double throw (spdt) analog switch that offers precise switching capability from a single 1.65v to 4.5v supply with low on-resistance (0.39 ) and high speed operation (t on =30ns, t off = 16ns). the device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65v), low power consumption (6.3w max), low leakage currents (165na max), and the tiny tqfn package. the ultra low on-resistance and ron flatness provide very low insertion loss and distortion to applications that require signal reproduction. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 8). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed, then precautions must be implemented to prohib it the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the v+ rail. logic inputs can be protected by adding a 1k resistor in series with the logic input (see figure 8). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. figure 4. off isolation test circuit figure 5. r on test circuit figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) analyzer r l signal generator v+ c 0v or v+ no or nc com in gnd v+ c 0v or v+ no or nc com in gnd v nx v 1 r on = v 1 /100ma 100ma 0v or v+ analyzer v+ c no or nc signal generator r l gnd in 1 com 50 n.c. com nc or no v+ c gnd no or nc com in impedance analyzer 0v or v+ isl54056
8 fn6357.1 october 30, 2006 this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins as shown in figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. these schottky diodes mu st be sized to handle the expected fault current. power-supply considerations the isl54056 construction is typical of most single supply cmos analog switches, in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 4v maximum supply voltage, the isl54056 4.7v maximum supply voltage provides plenty of room for the 10% tolerance of 4.3v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.65v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the electrical specification tables and ? typical performance? curves for details. v+ and gnd also power the internal logic and level shiftiers. the level shiftiers convert the input logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this family of switches c annot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. logic-level thresholds this switch family is 1.8v cmos compatible (0.5v and 1.4v) over a supply range of 3.0v to 4.5v (see figure 14). at 3.0v the v il level is about 0.53v. this is still above the 1.8v cmos guaranteed low output ma ximum level of 0.5v, but noise margin is reduced. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. the isl54056 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0v to v+). for example driving the device with 2.85v logic (0v to 2.85v) whil e operating with a 4.2v supply the device draws only 12 a of current (see figure 16 for v in =2.85v). high-frequency performance in 50 systems, the isl54056 has a -3db bandwidth of 104mhz (see figure 21). the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. figure 22 details the high off isolation and crosstalk rejection provided by this part. at 100khz, off isolation is about 65db in 50 systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog- signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage curren ts of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. figure 8. overvoltage protection gnd v com v nx v+ in x optional protection resistor optional schottky diode optional schottky diode isl54056
9 fn6357.1 october 30, 2006 typical performance curves t a = +25c, unless otherwise specified figure 9. on resistance vs supply voltage vs switch voltage figure 10. on resistance vs supply voltage vs switch voltage figure 11. on resistance vs supply voltage vs switch voltage figure 12. on resistance vs switch voltage figure 13. on resistance vs switch voltag e figure 14. on resistance vs switch voltage 012345 r on ( ) v com (v) i com = 100ma 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.4 v+ = 4.5v v+ = 4.3v v+ = 3.9v r on ( ) v com (v) 00.511.522.533.5 0.36 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46 i com = 100ma v+ = 3.3v v+ = 3v v+ = 2.7v 00.511.52 0.4 0.5 0.6 0.7 0.8 r on ( ) v com (v) i com = 100ma v+ = 2v v+ = 1.8v v+ = 1.65v 012345 0.25 0.3 0.35 0.4 0.45 r on ( ) v com (v) v+ = 4.3v i com = 100ma +85c -40c +25c 00.511.522.533.5 0.3 0.35 0.4 0.45 0.5 r on ( ) v com (v) +85c -40c v+ = 3.3v i com = 100ma +25c 00.511.522.53 0.3 0.35 0.4 0.45 0.5 0.55 r on ( ) v com (v) +85c -40c v+ = 2.7v +25c i com = 100ma isl54056
10 fn6357.1 october 30, 2006 figure 15. on resistance vs switch voltage figure 16. supply current vs vlogic voltage figure 17. charge injection vs swit ch voltage figure 18. digital sw itching point vs supply voltage figure 19. turn-on time vs supply voltage fi gure 20. turn-off time vs supply voltage typical performance curves t a = +25c, unless otherwise specified (continued) 00.511.52 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 r on ( ) v com (v) +85c -40c v+ = 1.8v i com = 100ma +25c i on ( a) v in1&2 (v) v+ = 4.2v 12345 0 50 100 150 200 sweeping both logic inputs q (pc) v com (v) -100 -50 0 50 100 150 200 250 012345 v+ = 1.8v v+ = 3v v+ = 4.3v v+ (v) v inh and v inl (v) 1.522.533.544.5 v inh v inl 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t on (ns) v+ (v) 11.522.533.544.5 0 50 100 150 200 250 +85 c -40 c +25 c t off (ns) v+ (v) 1 1.5 2 2.5 3 3.5 4 4.5 10 15 20 25 30 35 40 +85 c -40 c +25 c isl54056
11 fn6357.1 october 30, 2006 figure 21. frequency response figure 22. crosstalk and off isolation die characteristics substrate potential (powered up): gnd transistor count: 228 process: si gate cmos typical performance curves t a = +25c, unless otherwise specified (continued) frequency (hz) 0 -20 normalized gain (db) gain phase v+ = 3v 0 20 40 60 80 100 phase () 1m 10m 100m 600m v in = 0.2v p-p to 2v p-p r l = 50 frequency (hz) 1k 100k 1m 100m 500m 10k 10m -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation crosstalk v+ = 4.3v isl54056
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6357.1 october 30, 2006 isl54056 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0- 12 4 rev. 4 8/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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